module div_1000f
(
	input		SYS_RST_N,
	input		SYS_CLK,
	input		IN_P,
	output	reg	DIV1000_P
);

reg	[9:0]	div1000_r;

always @ (posedge SYS_CLK)
	if (~SYS_RST_N)
	begin
		div1000_r <= 9'd0;
		DIV1000_P <= 1'b0;
	end
	else 
	begin
		if (div1000_r < 999) 
		begin
			if (IN_P)
				div1000_r <= div1000_r + 1;
		end
		else
			div1000_r <= 0;	

		if (IN_P & (div1000_r == 998)) 
			DIV1000_P <= 1;
		else 
			DIV1000_P <= 0;
	end	
endmodule
